1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a CMOS integrated circuit having the structure for preventing the latch-up phenomenon.
2. Description of the Related Art
In a complementary MOS (CMOS) inverter circuit which is formed as a basic circuit element of CMOS integrated circuit, the drains of P-channel type MOS FET 36 and N-channel type MOS FET 37 are commonly connected to output terminal 38 as shown by block A in FIG. 6. The sources of P-channel type MOS FET 36 and N-channel type MOS FET 37 are respectively connected to power source terminal VDD 32 and GND terminal VSS 39. The gate of each MOS FET is connected to input terminal IN 11.
In order to prevent the gate of the CMOS FET from being damaged, gate protection diodes 35 and 34 are respectively connected between power source terminal VDD 32 and input terminal IN 11 and between input terminal IN 11 and GND terminal VSS 33 as shown by block B in FIG. 6.
FIG. 5 shows an example of the cross section of such CMOS integrated circuit device.
P-channel type MOS FET 36 includes P-type source 51, drain 52, and gate electrode 44 formed on a gate insulation film which is formed on that portion of the surface of substrate 14 which lies between the source and drain. N-channel type MOS FET 37 is formed in P-type well 43 which is formed in the surface area of substrate 14. N-channel type MOS FET 37 includes N-type source 50 and drain 53 formed in the surface area of well 43, and gate electrode 45 formed on a gate insulation film which is formed on that portion of the surface of well 43 which lies between the source and drain.
Protection diode 35 is formed to have substrate 14 acting as a cathode and P-type layer 46 formed in the surface area of substrate 14 to serve as an anode. Diode 34 is formed to have P-type well 47 formed in the surface area of substrate 14 to serve as an anode and N-type layer 48 formed in the surface area of well 47 to serve as a cathode.
For example, when a noise voltage higher than the voltage applied to power source terminal VDD 32 is introduced into input terminal IN 11 of the above MOS integrated circuit, current component I1 flows in the surface area of substrate 14 from P-type layer 46 acting as the anode of protection diode 35 to N-type layer 49 used as a substrate contact of P-channel type MOS FET 36. That is, protection diode 35 is forwardly biased and made conductive to lower the potential of the gate electrode of the CMOS FET to substantially VDD level, thus preventing the gate from being damaged. However, in this case, all the current does not flow into N-type contact layer 49, and current component I2 will flow in the bottom portion of substrate 14.
Current component I2 flows in the path of input terminal 11.fwdarw.P-type anode layer 46.fwdarw.N-type substrate 14.fwdarw.P-type well 43.fwdarw.N-type source 50.fwdarw.GND terminal 39. In the current path, a parasitic thyristor with four-layer PNPN structure is formed to have layer 46, substrate 14, well 43 and source 50. If current component I2 is negligible, the thyristor will not actually be turned on. However, if current component I2 becomes large, a so-called latch-up phenomenon occurs, making the parasitic thyristor operative. As a result, a conduction current flows continuously between power source terminal VDD and GND terminal VSS. Therefore, the normal operation of the MOS FET cannot be effected and the MOS FET may be damaged by heat which is generated by a large thyristor conduction current. Conventionally, in order to solve this problem, anode layer 46 of diode 35 is formed to be as far away as possible from well 43 of MOS FET 37 so as to suppress current component I2 to a minimum.
The same problem concerning the parasitic thyristor as described above occurs in the case of a combination of diode 34 and P-channel type MOS FET 36. Also in this case, it is necessary to set well 47 of diode 34 sufficiently far away from P-type source 51 of MOS FET 36. For example, in the conventional case, the distance between anode layer 46 of diode 35 and N-type contact layer 49 of P-channel type MOS FET 36 was set as large as 50 .mu.m. As a result, the occupied area of the CMOS integrated circuit becomes large, lowering the integration density.